1. Field of Use
The present invention relates to memories and more particularly to methods for improving the reliability of dynamic random access memories without requiring extensive testing.
2. Prior Art
It is well known to utilize error detection and correction (EDAC) schemes to make a memory system more reliable. In a typical scheme, the data bits of a word are supplemented by a plurality of check bits called EDAC bits. During each memory cycle of operation, the word is checked for errors and is corrected for single bit errors. The address of the location detected as having produced a single bit error may be flagged for maintenance purposes. Two bit errors and some other multiple bit errors are typically detected but not corrected. Thus, such schemes may not be effective in detecting and correcting multibit errors within a word.
In memory board construction, it is common practice to connect the plurality of memory devices such that like address weight bits are connected to the same respective input pin on each device. That is to say, if a given address bit is connected to address input pin n of the first of the plurality of memory devices, it is connected to address input pin n on the remainder of said devices. Exceptions to this rule are for purposes of efficiency and convenience of board layout and etch routing.
It is also a well known technique to utilize test patterns for testing static and dynamic random access memories (SRAMs and DRAMs, respectively) for detecting faults to ensure memory reliability. Some have used arrangements which include pseudo random pattern generators as address generators. However, it has been found that neither test patterns nor such pseudo random arrangements are able to detect all pattern sensitive faults. For the purpose of the present invention, pattern sensitivity refers to the undesirable relationship between different cells within an integrated circuit (IC) memory part.
The likelihood of a particular cell being "disturbed" is determined by the parts physical and electrical characteristics. Generic testing for pattern sensitive faults requires the use of special tests which involve an exceedingly large number of patterns. The time of such testing increases exponentially with memory size.
Testing time has become a concern since the introduction of large semiconductor memory devices, such as for example, 64K DRAM devices. As RAM devices increase in density and size, the cost of applying exhaustive pattern sensitivity tests becomes increasingly prohibitive. The larger the memory device, the less practical it becomes to fully test such part. That is, RAM devices with such large storage capacities require extended time periods for testing. To reduce the testing burden, some RAM devices have been designed to include built in test circuits enabling several different memory locations to be written with the same data. This type of arrangement is described in U.S. Pat. No. 4,811,299. While this can reduce the time for performing certain test operations, it still does not eliminate the need for the type of exhaustive testing required for detecting pattern sensitive faults.
It has been noted that there is a likelihood of pattern sensitivity similarities between memory parts having similar layouts and those manufactured as part of one or more groups or lots. Because of the importance of detecting such faults, it has been necessary to include circuits in memory testers for reconnecting address paths to those memory parts in which the internal addressing has been altered with respect to some norm which may be arbitrary (i.e., different layouts) to meet certain test development expectations for testing memory parts for pattern sensitivity. An example of one such circuit is disclosed in U.S. Pat. No. 4,782,488.
While the above schemes reduce the need for certain types of testing, a significant level of testing is still required for maintaining a high level of reliability. As RAM parts increase in size, the level of testing continues to increase.
While the prior art acknowledges the existence of pattern sensitivity problems, there has been no direct approach taken to lessen the impact of multiple errors occurring because of pattern sensitivity similarities amongst a group of RAM devices. The above discussed methods of detecting and logging errors only indirectly respond to the problem. Exhaustive testing of memory parts has been used only in the case of moderately dense memory parts because of time and cost considerations.
Accordingly, it is a primary object of the present invention to provide a memory system which does not require extensive testing for establishing reliability.
It is a further object of the present invention to provide a memory system which is tolerant of pattern sensitivities.